If only bumping is subcontracted, positioning the bumping step just after wafer fab means that wafers must be shipped to an outside supplier and then returned for wafer thickness reduction.
During this operation, the bumps must be protected either by a dedicated sticky foil on the front side or by a resist to be removed chemically after completion. Then, the front side of the wafer must be cleaned using plasma or chemical processing. This is needed to ensure that residues will not affect the adhesion of the underfill after flip chip attach, and to avoid any impact of potential residues on reliability. Bumping after electrical wafer sort EWS has an advantage over other alternatives.
It is not easy to electrically test bumped wafers because the soft bump materials can stick on the extremity of the probe. This can reduce EWS throughput because of the frequent cleaning that must be done on probes. Of course, EWS before bumping assumes that the bumping process is compatible with probing marks in the pads. Only a few processes allow such marks before bumping.
It is necessary to map the wafers electronically and make sure the electronic mapping format is compatible with the wafer inspection system to be used after bumping.
Performing bumping before EWS eliminates concerns about bumping on probe-marked pads. Bumping before EWS, however, requires that flip chip equipment be able to track good die using electronic mapping. Almost all die attach equipment, including flip chip bonders, can do this.
A final caveat is that any impact that the bumping process has on the electrical integrity of die cannot be detected if bumping is done after testing. Electrical testing on bumped wafers is, of course, a critical part of the bumping process. In the case of peripheral solder bumps and even a two-row staggered structure, a standard probing card configuration can be used. The probe design, including shape and material, can be optimized to minimize the downtime of probers and probe cleaning frequency.
In the case of an array of more than two rows, vertical probing card technology is needed to access bumps located in the center of the die. Vertical probing largely eliminates the problem of material sticking on probes Figures 6 and 7. On the other hand, the wiring needed for vertical probing limits testing frequency to not more than a few hundred megahertz.
Before choosing the testing technology, prober parameters, such as offset, speed, probe cleaning frequency and testing temperature range, should be considered. At high temperatures, solder alloys can soften, resulting in bump deformation. In addition, the cost of a vertical probing card is much higher than the cost of standard epoxy probing cards — up to 10 times higher depending on factors like configuration, pin count, supplier and production volumes.
In the case of RF bumped die that must be flip chip attached in a package and tested internally at high frequency before shipment, the test can be done after packaging. Prober offset can also be set to electrically detect missing bumps.
The bumping process introduces defects that are often detected by a visual inspection of wafers. Full percent optical inspection is expensive and can only be used if the cost of such an operation is in line with the cost target of the application or if the customer requires it. For volume production, inspection can be automated, making the use of statistical process control SPC possible.
Computerized results are both less costly and more reliable. So far, SPC is in use by only a few bumping service suppliers and many aspects of this approach are still being investigated.
Bumps must be measured to confirm that bump height is within specifications and to verify coplanarity of bumps within a single die.
This is essential to ensure that bumps are sufficiently coplanar to be compatible with the next steps of the flip chip process, including fluxing and contact with traces. This is especially important for gold bumps, which are much smaller than solder bumps and, therefore, more sensitive to bad coplanarity in such cases as flip chip in ACF.
A percent measurement operation can be time consuming; in one case requiring several hours to measure 40, solder bumps on a single wafer.
That makes a low-rate sampling approach a good compromise in terms of risk and time for this type of quality assurance QA. Fortunately, bumping processes are generally sufficiently consistent with respect to height and diameter so that percent measurement is not necessary. A few bumps measured on carefully chosen locations within the wafer should be enough. For bumping technology characterization, it is necessary to determine the range of bump height variations within a wafer, which depends on the bumping process type.
For example, electroplating processes provide systematically smaller bumps at the center of the wafer, compared to the edges, because of the electrical resistance of the seed layer used to polarize the bump sites. X-ray control is a good way to make sure that bumps are relatively void-free and that the voids are within specification.
Today, void-free bumping processes do not exist and the commonly agreed specification is an X-ray-verified void diameter that is no more than 30 percent of bump diameter. This specification has limited utility because, after reflow, bump diameter is no longer a reference.
The appropriate parameter is either the UBM size or the passivation opening. Because this void specification issue is still an open question, it is mandatory to have X-ray equipment able to detect voids as small as 10 microns. In addition, all equipment dedicated to controls or visual inspections must be compatible with wafer mapping.
Qualification of a bumped product can be done in several different ways. The bumps themselves can be qualified independent of the application, with the customer taking care of the qualification of the final flip chipped product.
In this case, the bumping qualification will be focused on bumping process as well as on bump structure and evolution of the structure intermetallic layer, for example , shear tests vs.
Bumps can be qualified directly on the application, if necessary. Impact of stress because of the application itself substrate material, underfill can only be measured for qualification purpose after the flip chip process.
On the other hand, it doesn't make sense to qualify bumps independently of the application board, because those tests are often dependent on temperature variations and thermal expansion.
The reliability of a flip chip connection depends on the temperature range of the application, bump material and structure, bumping and flip chip processes as well as materials, such as flux, underfill and substrate. The global yield and reliability of any application also depends on the number of devices, both silicon die and passive components, mounted on the application.
The final customer often requests a quality assessment, sometimes including reliability tests at die level. The decision to develop such a process is strongly dependent on its impact on the global cost of the application. That, in turn, is linked to factors like complexity, number of devices integrated in the application and market segment. The approach will be different for an application on which only one small die is flipped on a low-cost single layer board, compared to a flip chip multi-chip module on which passive components are mounted and integrated in a very complex and high-density PCB.
Failure analysis isn't easy, as the die is flipped and often sealed in underfill material or molding compound. One method uses non-destructive methods employing analysis tools like X-rays to allow checking several points while maintaining the integrity of the assembly. There is no chemical or mechanical failure analysis process that can make further analysis easy.
Sonic acoustic microscopy can help, but today's transducers have insufficient resolution and sensitivity to reliably detect voids or bridges through silicon and assembly materials substrate, underfill. Furthermore, resolution is still not good enough to accurately detect delamination at the UBM interface. Destructive analysis involving removal of materials with chemicals, plasma or mechanical processes sometimes.
Both destructive and non-destructive methods can be used advantageously. How this should be done depends on target cost and on the market segment of the end product. Lau and Y. Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share. Bumping Options Ramping up for delivery of bumped bare die can be a daunting task for manufacturers.
Figure 1. Bumping technology alternatives. Click here to enlarge image There are different configurations to evaluate and choose from and the chosen alternative must be integrated into a well-optimized process flow. A Closer Look There are five basic types of bumping processes in use today: solder stencil printing Figure 2 , solder screen printing Figure 3 , solder or gold electrolytic deposition Figure 4 , gold stud bumping and sputtering.
Figure 2. Solder stencil printing process during solder paste deposition. Click here to enlarge image One key factor in choosing the best bumping technology is the application board or PCB itself because its minimum design rules must be compatible with the defined bumping pitch of the process.
Figure 3. Solder screen printing process during solder paste deposition. Click here to enlarge image Gold electrolytic bumping is one process that is widely available and used extensively.
Figure 4. Solder electroplating process after solder or gold electrolytic deposition. Click here to enlarge image When bumping is outsourced, multi-sourcing concerns become important. RDL Pros and Cons RDLs are formed by adding passivation and metal layers on the top of the die, relocating the pads according to the design rules of the solder bumping process Figure 5.
Figure 5. Redistributed bumped die. Click here to enlarge image The design rules generally recommended today include a peripheral pitch of microns and an array pitch of microns. Process Flow Constraints When bumping is integrated into a volume production operation, the process flow has to be planned carefully to avoid dramatic increases in costs and cycle time, as well as reduced yield. Figure 6. Bump is an original concept — both an immediate warning to wearers if they get too close, and a generator of management information to improve safety and business performance.
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